1. Technical Field
The embodiments described herein relate to a delay locked loop circuit (DLL circuit), and in particular, to a locking state detector that detects the locking state and a DLL circuit including the same.
2. Related Art
Generally, a DLL circuit is used to provide an internal clock signal whose phase is faster than that of a reference clock signal, and is obtained by converting an external clock signal by a predetermined time period. Specifically, the DLL circuit is used to solve the problem of prolonged output data access time, wherein the internal clock signal used in a semiconductor circuit is delayed while passing through a clock buffer and along a transmission line causing a phase difference from the external clock signal. The DLL circuit controls the phase of the internal clock signal to be faster than the phase of the external clock signal by a predetermined time in order to increase the effective data output interval.
The DLL circuit is commonly arranged having a feedback loop configuration, and includes a delay line that delays a reference clock signal transmitted from a clock input buffer in response to a delay control signal to generate a delay clock signal, a replica delayer that delays the delay clock signal with a delay value that is obtained by modeling a delay amount by delay elements presented in the output path of the delay clock signal to generate the feedback clock signal, a phase detecting block that compares and detects phases of the reference clock signal and the feedback clock signal to generate a phase detecting signal, and a delay controlling block that generates a delay control signal in response to the phase detecting signal.
In addition, the DLL circuit further includes a locking state detector that enables a locking state signal, which indicates the completion of the delay locking operation when the phase difference between the reference clock signal and the feedback clock signal is reduced below a predetermined range. If the locking state signal is enabled, then the delay controlling block adjusts the number of unit delays activated in the delay line to stop the changing of the delay value.
Generally, the external clock signal that is input to the DLL circuit includes a jitter component, that effects the toggle timing or the pulse width of the external clock signal. If the jitter is generated in the external clock signal it can cause the phase of the reference clock to change. When this occurs, the phase difference between the reference clock signal and the feedback clock signal instantaneously exceeds the predetermined range. The locking state detector is configured to disable the locking state signal whenever the above phenomenon occurs. Therefore, the enable state of the locking state signal is frequently changed by the jitter of the external clock signal, which causes the DLL circuit to, e.g., frequently change of the operation mode. As a result, the internal clock signal cannot be stably generated. Furthermore, because the stability of the operation of the DLL circuit is reduced, a semiconductor integrated circuit (IC) that uses the DLL circuit is not suitable for stable operation.